1. Field of the Invention
The present invention relates to a binary data converter, and more particularly to a device for converting a positive binary data into a negative binary data represented by a complement on two (2) and vice versa.
2. Description of Prior Art
As is well known, representation by a complement on two of a binary data has been utilized in processing units such as computers for simplifying subtraction processing. Now, the representation by the complement on two will be briefly described. In an operation for converting a certain binary data into the two's complement (i.e. complement on two) data, all bits in the binary data are inverted, and then one is added to a least significant bit. For example, when a binary data of 4 bits "0101" (=+5) is converted into the two's complement data, it become "1011" (=-5). In this data, a most significant bit thereof is treated as a sign bit for indicating whether the data is positive of negative. Thus, if the sign bit is "0", it indicates that a value of the data is positive, and if it is "1", it indicates that the value of the data is negative. The representation by a complement on two has been usually utilized only for representing the data having a negative value. Therefore, if the data of a positive value is required for the processing, a positive binary data itself including a sign bit of "0" is utilized without inversion.
In a course of operation of the binary data, it is sometimes required to convert a positive binary data into a negative binary data represented by the complement on two and vice verse. In order to enable these conversions, binary data converters, e.g., as shown in FIG. 3 have been proposed.
FIG. 3 is a block diagram illustrating a binary data converter of 4 bits, which is disclosed in "Logic Design of Digital Systems" by Donald L. Dietmeyer, p207, FIG. 3.32 "two's Complement Arithmetic System ADPSUB2c". In the figure, input terminals 1a-1d receive positive binary data or negative binary data represented by a complement on two. The binary data of 4 bits inputted through the input terminals 1a-1d is inverted by the inverters 2a-2d and is inputted into one input X of each of half adders 3a-3d. The other input Y of each of the half adders 3a-3d receives carry outputs from the preceding half adders, respectively. The input Y of the half adder 3a at the first stage constantly receives "1". Outputs from the half adders 3a-3d are applied to output terminals 4a-4d, respectively. Converted binary data is introduced through the output terminals 4a-4d. The output terminal 4e to which the half adder 3d at the last stage applies the carry output is not generally used.
Operations of the conventional binary data converter shown in FIG. 3 is as follows. It is assumed that a positive binary data "0101" (=+5) of 4 bits is to be converted into a negative binary data represented by the complement on two. As shown in FIG. 3, the all four bits of the binary data "0101" inputted into the input terminals 1a-1d are inverted by the inverters 2a-2d and "1010" is resulted therefrom. The inverted bit signals are applied to one input X of each of the half adders 3a-3d,, respectively. Therefore, "0" is inputted to the input X of the half adder 3a for the least significant bit. "1" is constantly applied to the other input Y of this half adder 3a. Thus, the half adder 3a performs a following operation. EQU 0+1=1(carry output "0")
Consequently, the output terminal 4a outputs "1". In the carry output "0" of the half adder 3a is inputted to the input Y of the half adder 3b at the next stage. Similar operations are performed in the half adders 3b-3d, and consequently, the negative binary data "1011" (=-5) represented by the complement on two is outputted form the output terminals 4a-4d.
Each of the half adders 3a-3d shown in FIG. 3 consist of an AND gate 6 and an exclusive OR circuit 7, as shown in FIG. 4. The AND gate 6 shown in FIG. 4 consists of a NAND gate 61 and an inverter 62, as shown in FIG. 5. The exclusive OR circuit 7 consists o two inverters 71 and 72 and two transmission gates 73 and 74.
The conventional binary data converter circuit thus constructed has such a problem that delay of signals due to the carry outputs from the half adders is caused, resulting in a slow operation speed. Further, since the conventional binary data converter circuit employs the half adders having complicated structures as shown in FIGS. 4 and 5, it requires many transistors, resulting in an expensive circuit. More specifically, (16.times.n) transistors are required in the binary data converter circuit in which the binary data of n bits is processed on a principle illustrated in FIG. 3. Therefore, each half adder of 4 bits shown in FIG. 3 requires 64 (=16.times.4) transistors.